In present semiconductor technology, complementary metal oxide semiconductor (CMOS) devices, such as nFETs (i.e., n-channel MOSFETs) or pFETs (i.e., p-channel MOSFETs), are typically fabricated upon semiconductor wafers, such as Si, that have a single crystal orientation. In particular, most of today's semiconductor devices are built upon Si having a (100) crystal orientation.
Electrons are known to have a high mobility for a (100) Si surface orientation, but holes are known to have high mobility for a (110) surface orientation. That is, hole mobility values on (100) Si are roughly 2×-4× lower than the corresponding electron mobility for this crystallographic orientation. To compensate for this discrepancy, pFETs are typically designed with larger widths in order to balance pull-up currents against the nFET pull-down currents and achieve uniform circuit switching. pFETs having larger widths are undesirable since they take up a significant amount of chip area.
On the other hand, hole mobilities on (110) Si are 2× higher than on (100) Si; therefore, pFETs formed on a (110) surface will exhibit significantly higher drive currents than pFETs formed on a (100) surface. Unfortunately, electron mobilities on (110) Si surfaces are significantly degraded compared to (100) Si surfaces.
As can be deduced from the above, the (110) Si surface is optimal for pFET devices because of excellent hole mobility, yet such a crystal orientation is completely inappropriate for nFET devices. Instead, the (100) Si surface is optimal for nFET devices since that crystal orientation favors electron mobility.
Methods have been proposed to form such an integrated semiconductor device in which both the nFETs and the pFETs are formed on a same substrate having different crystallographic orientations.
For example, co-assigned U.S. Pat. No. 6,998,684, the disclosure of which is hereby incorporated by reference in its entirety, discloses an integrated circuit structure that has a substrate having at least two types of crystalline orientations, in which first-type transistors (e.g. NFETs) are formed on first portions of the substrate having a first type of crystalline orientation, and second-type transistors (e.g. PFETs) are formed on second portions of the substrate having a second type of crystalline orientation.
One challenge encountered in the formation of such hybrid orientation technology (HOT) devices occurs during the formation of the shallow trench isolation (STI) structures, formed to isolate the devices formed in portions of the substrate having the first type of crystalline orientation from devices formed in portions of the substrate having the second type of crystalline orientation. In particular, the formation of the trench may require controlled etching of multiple materials in a single process step, for example, when the HOT devices are formed on bulk crystalline semiconductor portion adjacent an SOI portion, which may be difficult to control, and may lead to defects that impact yield.
For the reasons discussed above, it would be desirable to form HOT semiconductor device including isolation regions between bulk and SOI devices that uses a more controllable process that will lead to improved yield.